1. Technical Field
The present invention relates to a test apparatus and a test method. The invention relates to, in particular, a test apparatus for testing a device under test and a test method thereof.
2. Related Art
Semiconductor memory such as DRAM can perform a burst transfer in which pieces of data can be uninterruptedly transferred based on information of one address. Japanese Patent Application Publication H.9-43317 (Patent Document 1) is an example of related art. Patent Document 1 discloses a test apparatus testing such semiconductor memory.
A pattern generator provided in the test apparatus described in Patent Document 1 generates a main pattern at a low-speed test cycle and concurrently generates a plurality of sub-patterns for the main pattern at each generation of the main pattern. The pattern generator then multiplexes the plurality of sub-pattern and outputs them.
The test apparatus equipped with such pattern generator can supply data to a memory under test at a high transfer rate while it operates at a low-speed test cycle.
The pattern generator described in Patent Document 1 generates sub-patterns for an initial segment cycle of the test cycle by just delaying the main pattern. When such pattern generator generates a test pattern for the burst transfer, the test apparatus has to run an test program which is adjusted, by inserting a dummy cycle and so forth, to generate initial sub-patterns of the burst transfer are generated in the initial segment cycle of the test cycle. Thus, testing performed by the test apparatus of Patent Document 1 takes a long period, and design freedom of test programs is limited.